ANANYA GOWDA

RTL Design and Verification Engineer (Fresher) with hands-on experience in Verilog/SystemVerilog-based digital design and functional verification. Strong understanding of FSM design, synchronous design principles, SPI protocol implementation, and dual-port RAM architecture. Experienced in developing self-checking testbenches, assertions, and simulation-based debugging using industry-standard EDA tools. Seeking an entry-level opportunity in Front-End VLSI Design or Functional Verification.